The present invention relates to a high resolution clock circuit and to a method of generating a high resolution clock output from a lower resolution clock input and especially to a clock circuit using conventional technology and a plurality of delay lines. Many conventional clock circuits are based on the frequency of an accurate crystal oscillator. When using conventional digital circuits with a crystal oscillator to measure time, the shortest length of time that can be resolved is the period of the clock. Some military applications require high resolution to within 0.5 nanoseconds (nsec.). If conventional circuits, such as counters or shift registers are used to generate the time codes, then the clock frequency should be 2 GHz. Crystal controlled, 2 GHz frequency sources are readily available. The only kind of logic circuits that can operate at 2 GHz are those using the gallium arsenide (GaAS) process. GaAs technology is expensive because a custom circuit must be designed and fabricated on a single chip. This requires a large investment of money and time. The fastest conventional logic family is the F100K emitter coupled logic (ECL) and can operate at speeds of 0.2 GHz over the military temperature range. This is a factor of ten too slow to construct a conventional clock with a 0.5 nsec. resolution.
Prior U.S. patents of interest include the Butcher U.S. Pat. No. 4,847,870, for a high resolution digital phase-lock loop circuit which is implemented with an input clock reference frequency which is approximately the same as the output frequency of the phase-lock loop. The output is derived from delaying the input clock a variable number of gate delays ranging from no delay to one period of the input clock. A shift register controls the number of gate delays. The Shaffer et al. U.S. Pat. No. 5,235,699, is a circuit that controls, calibrates, and monitors critical timing parameters in a computer system or a network to prevent loss of or inaccurate data when transferring the data. The Kabuo et al. U.S. Pat. No. 5,247,656, is a method and apparatus for controlling a clock signal for data processing devices and includes first and second blocks which have different processing times and which operate in synchronism with a clock signal. A period of the clock signal is changed in accordance with the clock change signal. The Boris et al. U.S. Pat. No. 4,989,175, is a high speed on-chip clock phase generating system for mainframe computers and is incorporated into very large scale integrated logic chips. Each logic chip is controlled by off-chip control signals. The off-chip phase generator includes a start shift register, a stop shift register, clock shift registers to provide the phase of the clock, and start/stop run controls, all of which are coupled to off-chip control signals and synchronized to eliminate distortion and skew between phase generators on different logic chips.
The present invention is for a delay line clock with sub-nanosecond resolution from a low resolution clock frequency using a set of different length delay lines to subdivide the low resolution clock period. The different length delay lines and ECL circuit can generate a sub-nanosecond resolution from a 100 MHz. clock input using conventional technology.